1. Field of the Invention
The present invention relates to a semiconductor memory device having a word line driver circuit, and more particularly to a word line driver circuit and a plate line driver circuit having stages and a reduced chip area.
2. Description of the Related Art
A semiconductor memory device operating at a low voltage generally employs a voltage boosting circuit to apply a voltage higher than the nominal supply voltage so as to increase the operating speed and the reliability of reading or writing data in a memory cell. In this manner, a voltage corresponding to data applied to a bit line is transferred to a capacitor of a memory cell without a drop of threshold voltage in an access transistor of a memory cell, or data (charge) stored in the capacitor is passed to the bit line without a drop of threshold voltage of the access transistor, to prevent or substantially reduce errors in read or write operations.
In such a semiconductor memory device a word line driver circuit constructed of a boosting circuit is generally used to apply a voltage level higher than the power supply voltage VDD, to a word line.
FIG. 1 is a circuit diagram illustrating a conventional word line driver circuit for use in a ferroelectric random access memory (FRAM).
Referring to FIG. 1, a conventional word line driver circuit includes four transistors N1, N2, N3 and N4, and has three control signals (lines) SWL_PDb, SWL_PD and SWL_DRV in addition to a main word line MWL and outputs a voltage to a sub word line SWL.
The word line driver circuit is configured so that a main word line enable signal (an output signal of word line decoding circuit, not shown) on the main word line MWL is transferred (passed) to a gate of a transistor N1 through a pass transistor N2, thus turning ON the transistor N1. The transistor N1 is configured to transfer (pass) the control signal SWL_DRV (that has a level of an external power supply voltage VPP having a level higher than the power supply voltage VDD), to a sub word line SWL connected to (access transistors of) a plurality of memory cells. The sub word line SWL is connected to a discharge transistor N4 that is controlled by control signal SWL_PDb, to prevent floating of the sub word line.
All control signals shown in FIG. 1 except the control signal SWL_PDb are maintained at a ground voltage level (Vss, 0V), before the main word line enable signal is applied. When a read or write operation starts, a main word line enable signal is applied (at a power supply voltage level VDD) to a selected main word line MWL. Then, a node voltage (on the node between the transistor N2 and the transistor N1) at the gate of transistor N1, increases to a voltage level VDD−Vth obtained by subtracting the threshold voltage Vth of the transistor N2 from the power supply voltage level VDD. After a while, when a control signal SWL_DRV is applied at an external power supply voltage level VPP, the node voltage is boosted to VCC−Vth+VPP by a capacitance between the drain and the gate of the transistor N1. Hence, the transistor N1 has the sufficient gate voltage VCC−Vth+VPP, and a voltage level VPP (of the control signal SWL_DRV at the external power supply voltage level VPP) is supplied to a sub word line SWL without a drop of threshold voltage of the transistor N1. Thus an access transistor of a memory cell (CELL) connected to the sub word line SWL operates by a sub word line enable signal at the external power supply voltage level VPP, without error.
The control signal SWL_PD is applied to drive the transistor N3 at a voltage having the power supply voltage level VDD, to prevent floating of a sub word line of a word line driver circuit that is not selected among the plurality of word line driver circuits.
FIG. 2 is a block diagram illustrating the layout of a semiconductor memory device having the conventional word line driver circuit of FIG. 1.
With reference to FIG. 2, a plurality of conventional word line driver circuits SWD 10 are connected, in parallel, to a main word line MWL, and each word line driver circuit 10 is connected to every memory CELL in a memory cell array 20 by one sub word line SWL (e.g., SWL0).
In a semiconductor memory device having such a conventional word line driver circuit, the number of memory cells to be controlled by one word line driver circuit SWD 10 on an integrated chip may be limited by the parasitic capacitance of each sub word line. Each unit of length of sub word line has an associated parasitic capacitance and also each of the memory cells connected to the sub word line adds a gate capacitance to the parasitic capacitance of the sub word line. Thus, for driving a large number of memory cells on a chip, a large number of word line driver circuits are required, and the number of memory cells that can be controlled by each word line driver circuit is limited.
As previously noted, the conventional word line driver circuit shown in FIG. 1 is constructed of four transistors (switches) and so in using a large number of word line driver circuits, significant layout area is required on the chip, causing an increase of chip size.
FIG. 3 illustrates a conventional word line driver and plate line driver circuit SWPD 40 for use in a ferroelectric random access memory (FRAM).
As shown in FIG. 3, the word line driver and plate line driver circuit SWPD 40 is configured as one unit, including a conventional plate line driver circuit 30 and the conventional word line driver circuit 10 of FIG. 1.
In the conventional plate line driver circuit 30, when a main word line enable signal is applied (by MWL), a voltage boosting operation of transistor N6 and transistor N5 occurs as in the word line driver circuit 10 (of FIG. 1). Then, a control signal SPL_DRV is supplied, at a power supply voltage level VDD, as a plate line enable signal to a plate line SPL without a drop of the threshold voltage of the transistor N5, to operate (read or write) a memory cell.
The transistor N7 prevents floating of the plate line SPL when a main word line disable signal is applied on the main word line (MWL).
FIG. 4 is a block diagram illustrating the layout of a FRAM having a plurality of the conventional word line driver and plate line driver circuits SWPD 40 of FIG. 3.
Referring to FIG. 4, a plurality of conventional word line driver and plate line driver circuits SWPD 40 are connected, in parallel to each other, to a main word line MWL, and each word line driver and plate line driver circuit SWPD 40 is connected to a memory cell array through a sub word line (SWL0) and a plate line (SPL0).
The word line driver and plate line driver circuit SWPD 40 drives ferroelectric memory cells. The number of memory cells connectable to one word line SWL and plate line SPL is limited. Therefore, in a highly-integrated semiconductor memory device, several word line driver and plate line driver circuits 40 are needed, which occupies significant layout area, causing an increase of chip size.